1. Field of the Invention
The present invention relates to a signal processing circuit for a television camera using a solid-state image sensor.
2. Description of the Prior Art
Recently, a solid-state camera consisting of a semiconductor integrated circuit has been developed, instead of a camera tube used in the past, as an imaging device such as a television camera. One example of the solid-state camera is described and shown in "IEEE Spectrum, March 1969, P. 52-64". FIG. 1 schematically shows a sensor of such a solid-state camera. In this FIG. 1 denotes a horizontal scanning circuit, 2 denotes a vertical scanning circuit, 3 (3(m, n), 3 (m, n+1) . . . ) denote a plurality of photodiodes operating as photoelectric conversion devices, which are arranged like a matrix in a solid-state image sensor, 4 (4(m, n), 4(m, n+1) . . . ) denote vertical switching MOS transistors which are arranged similarly to the photodiodes and a source of each of which is connected to a cathode of a corresponding one of the photodiodes, 5 (5n, 5n+1, . . . ) denote horizontal switching MOS transistors, each of which is provided for corresponding to one row of a matrix array of the photodiodes 3, 6 (6m, 6m+1 . . . ) denote vertical scanning lines which are provided in correspondence with lines of the matrix array of the photodiodes 3 and each of which is connected to a gate of the MOS transistor 4 of a corresponding one line of the matrix array of the photodiodes, 7 (7n, 7n+1, . . . ) denote vertical scanning lines which are provided in correspondence with the MOS transistors 5 and each of which is connected to a gate of corresponding one of the MOS transistors 5, 8 (8n, 8n+1, . . . ) denote vertical scanning lines which are provided in correspondence with rows of the matrix array of the photodiodes 3 and each of which is connected to a source of the MOS transistor 5 and a drain of the MOS transistors 4 of corresponding one row, and 9 denotes a horizontal signal line connected to a drain of the MOS transistors 5, where suffixes n, n+1, etc. mean n-row, (n+1)-row, etc. respectively, and suffixes m, m+1, etc. mean m-line, (m+1)-line, etc. respectively. The photodiodes 3 and the MOS transistors 4 and 5 compose a solid-state image sensor.
An outline of a signal reading method of the solid-state camera described above will now be described. Each of the photodiodes 3 which are arranged like a matrix receives optical image light and stores photoelectrons in its junction capacitance in accordance with the quantity of light received. When the vertical scanning circuit 2 generates a positive scanning pulse V.sub.sy(n) shown in FIG. 2(a) on the vertical scanning line 6m, a row of the vertical switching MOS transistors 4 (m, n), 4 (m, n+1) . . . connected thereto are turned on. Subsequently, when the horizontal scanning circuit 1 generates a positive scanning pulse V.sub.sx(m) shown in FIG. 2(c) on the horizontal scanning line 7n, the horizontal switching MOS transistor 5n is turned on and therefore the photoelectrons stored in the photodiodes are brought through the MOS transistor 5n to an output terminal 14 so that a video signal is obtained. A predetermined time later, when a positive scanning pulse V.sub.sx(m+1) shown in FIG. 2(a) is supplied on the horizontal scanning line 7n+1, the horizontal switching MOS transistor 5n+1 is turned on so that the photoelectrons stored in the photodiodes 3(m, n+1) are brought to the output terminals. When sequential reading of the photodiodes of the m-th line in the manner described above has been terminated, a vertical scanning pulse V.sub.sy(n+1) shown in FIG. 2(b) is supplied on the vertical scanning line 6m+1 instead of said vertical scanning pulse V.sub. sy(n) being supplied on the vertical scanning line 6m. Thus, the photoelectrons stored in the photodiodes 3(m+1, n), 3(m+1, n+1) are read out sequentially by horizontal scanning similar to that described above. The photoelectrons stored in all of the photodiodes are read out by sequentially repeating the vertical scanning and the horizontal scanning similar to those described above.
FIG. 3(a) shows a waveform of the horizontal scanning pulse V.sub.sy(n) applied to a gate of the horizontal switching MOS transistor 5n of the n-th row. FIG. 3(b) shows a waveform of the horizontal scanning pulse V.sub.sy(n+1) applied to a gate of the horizontal switching MOS transistor 5n+1 of the (n+1)-th row. FIG. 3(c) shows a signal waveform obtained at the output terminal 14 (see FIG. 1). Spike-like voltage transistors 17n, 17n+1 and 18n, 18n+1, which are referred as spike noises, are generated such a manner that the horizontal scanning pulses are differentiated by parasitic capacitor 10n, 10n+1, etc. between the horizontal signal line 9 and the horizontal scanning line 7n, 7n+1, etc. or the MOS transistors 5n, 5n+1, etc. and transmitted along the horizontal signal line 9. A dotted line 19n, 19n+1 show signal waveforms obtained at the output terminal 14 in the case where video signal charges are provided, and an oblique line part denotes a video signal component.
If the spike noise at every scanning point always has a constant shape, the frequency components of the spike noise consist of only a repetition frequency thereof and its higher harmonic frequencies which are higher than frequency components of the video signal. Therefore, such a noise can be readily removed and thus its adverse effect on the video signal is little.
However, the amplitude and the shape of the spike noise, in fact, are largely varied with changing of the horizontal scanning pulse waveform V.sub.sy(n), V.sub.sy(n+1) and with variation of the parasitic capacitance 10n, 10n+1, accordingly a waveform similar to an amplitude modulated wave as shown in FIG. 4 is adversely provided. However, since this waveform is different from a normal amplitude modulated wave so that a carrier frequency (it corresponds to the repetition frequency) is adjacent to a modulation frequency (a frequency by which the spike noise waveform is varied), there is a time lag between an envelope 20 of a positive spike noise and an envelope 21 of a negative spike noise. Accordingly lower frequency components than the repetition frequency of the spike noise are included as shown by a dotted line 22. Since the bandwidth of the lower frequency components is the same as that of the video signal, the lower frequency components can not be removed by a low-pass filter so that they interfere with the video signal as a false signal. Particularly, the false signal is commonly superimposed on output signals of rows of photodiodes 3(m, n), 3(m+1, n) . . . ; 3(m, n+1), 3(m+1, n+1) . . . commonly connected to the vertical signal lines 8n, 8n+1 respectively so that it appears as a noise forming a fixed pattern of vertical stripes on a produced picture. This noise is so conspicious that quality of the produced picture is largely degraded.
In view of the above, a signal processing circuit employing an integrating circuit system has been provided for removing the fixed pattern noise. An example of such a signal processing circuit is described and shown in "IEEE International Solid-State Circuit Conference, Feb. 16, 1972, p. 30-31". FIG. 5 shows an integrating circuit which operates similarly to just before described example. In this figure, 23 denotes a sensor of the solid state camera described in connection with FIG. 1, 24 denotes an amplifier, 27 denotes an integrating capacitor, 28 denotes a MOS transistor used as a reset switch for integrating, 29 denotes a load resistor, 30 denotes a DC source, 31 denotes a terminal to which a reset pulse is to be applied, and 32 denotes a signals output terminal. The transistor 25 and an emitter resistor 26 comprise a common emitter amplifier, FIG. 6 shows an operating voltage waveform or an operating current waveform of an essential part of the circuit shown in FIG. 5. Operation of the circuit will now be described using this figure. A signal whose waveform is shown in FIG. 6(a) is applied through the amplifier 24 to a base of the transistor 25 from the sensor 23. Although, exactly speaking, spike noise couples, each of which is consisted of a positive spike and a negative spike which follows the positive spike, are different in their magnitude and shape as described in connection with FIG. 4, the spike noise is shown by a waveform having constant magnitude and shape to avoid complexity. In order for the transistor 25 to operate with good linearity, an appropriate DC bias voltage is superimposed on the output from the sensor part by the amplifier 24. FIG. 6(a) shows a waveform which is obtained from such a superimposing. FIG. 6(b) shows a waveform of a reset pulse which turn the MOS transistor or the integrating reset switch 28 on when the reset pulse is high, and which turn the MOS transistor 28 off when the reset pulse is low. The reset pulse has the same frequency as that of the horizontal scanning pulse shown in FIGS. 2(c), (d), and has a predetermined phase relation with the horizontal scanning pulse.
It is assumed that the MOS transistor 28 has been turned on before the time tn. The integrating capacitor 27 is charged to a voltage V.sub.A of the power source 30 with taking no account of a voltage drop of the load resistor 29. When the transistor 28 is turned off at the time tn, the charges stored in the integrating capacitor 27 are discharged through the transistor 25. At this time, a base of the transistor 25 is biased by a voltage shown in FIG. 6(a) so that the discharged current is a current controlled by the waveform shown in FIG. 6(a). Accordingly, a voltage across the integrating capacitor 27 (a collector voltage of the transistor 25) is reduced along a waveform shown in FIG. 6(c). In FIG. 6(c), a solid line 34 denotes the voltage across the capacitor 27 in the case where a signal applied to the base of the transistor 25 is consisted of only the spike noise, and a dotted line 35 denotes the voltage across the capacitor 27 in the case where the spike noise is superimposed on the video signal.
A value of a voltage drop of the capacitor 27 is proportional to the value of an integrating of the collector current of the transistor 25 between the time equals tn and the time equals t'n or the summation of the discharged charges between the time equals tn and the time equals t'n, and is inversely proportional to the capacitance value of the integrating capacitor. If a start point tn and an end point t'n of an integrating period is determined so that both of the positive spike noise component 17n and the negative spike noise component 18n are completely involved, the positive spike component and the negative spike component which is adjacent to the positive spike are cancelled each other to become zero by integrating because of the positive spike component level being the same as the negative component. Therefore, the sum of the discharged charges is not influenced by the spike noise. The integrating value becomes the sum of the value due to the DC bias current for the transistor and the value due to signal current component 19n.
Next, when the integrating reset switch is turned on at the time t'n, the integrating capacitor 27 is again charged through the load resistor to the voltage V.sub.A of the power source 30 so that the quantity of charged charges is approximately equal to the charges discharged during the period between tn and t'n (more precisely, a current which flows the transistor 25 during the period between t'n and tn+1 is involved). Therefore, the signal component without the spike noise component can be obtained by taking out this charging current (curve 36 of FIG. 6(d)) as a voltage drop of the load resistor 29. In FIG. 6(d), 36 denotes a waveform of the charging current in the case where the output of the amplifier 24 contains only the DC bias component but no the video signal component, a dotted line 35 denote a waveform of the charging current in the case where the video signal component is also contained. Therefore, the video signal is lower components (average value of dotted line 37) which are obtained by passing the waveform shown in FIG. 6(d) through a low-pass filter.
While the operating principle of the signal processing circuit has been described, attention should be made on the following matters. First, to make spike noise cancelling effect higher, the end point t'n of the integrating period should be delayed as much as possible. Second, since the interval between the end point t'n and a subsequent start point t.sub.n+1 becomes shorter because of delaying the point t'n, resetting of the integrating (charging of the integrating capacitor) is not sufficiently occured so that the output signal components of adjacent photodiodes of the same line may be interferred with each other so as to degrade the resolution. To avoid this, it is required that the load resistor 29 is properly selected to lower value, the resistance of the MOS transistor 28 or the reset switch when the transistor 28 is on is sufficiently low and a time constant of the charging circuit becomes shorter. Further, it is required that a switching time of the transistor 28 is sufficiently short. Above described signal processing circuit according to prior art has the following drawbacks.
First, a waveform of the signal which appears on the output terminal 32 is like a pulse wave with small duty ratio (as shown in FIG. 6(d)) which the quantity of a constant component due to the DC bias current component is larger than the quantity of the video signal component (transition component of the magnitude of the pulse 36 corresponding to the difference between the waves 36 and 37). Therefore, to extract only the signal component, a low-pass filter with good attenuating characteristic is required. Further, this low-pass filter should be disposed just behind the output terminal 32 for the reason why if the signal is directly supplied to a next stage amplifier without passing the signal through the low-pass filter, the amplifier is immediately saturated in response to the application thereof. This is a serious obstacle to integrated the circuit. Further, in order to fabricate the low-pass filter with good attenuating characteristic, it is required that inductances and capacitances used in the filter is large so that it is difficult to integrate the circuit.
Second, a noise voltage contained in the reset pulse 33 is transmitted through a parasitic capacitance between electrodes of the integration reset switching MOS transistor 28 or a mutual conductance of the transistor 28 to the signal line so that a signal to noise ratio of the video signal becomes lower. The transmission manner of the noise voltage is extremely complicated so that quantative analysis is difficult. However, in accordance with experiments, it has been found that the degradation of the signal to noise ratio is not negligible in the case where the magnitude of the signal component is about 100 mV in peak-to-peak value. Although, the noise of the type is theoretically suppressed by removing the noise contained in the integrating reset pulse 33, in fact it is difficult to remove the noise in the reset pulse completely and thus the trailing edge of the pulse in particular contains a considerable amount of noise.